A direct access storage device (DASD) is an on-line digital storage device, such as a magnetic disk drive, that allows rapid read and write operations. Often, DASD systems include more than one disk for increased reliability and crash recovery. Such a system can be a redundant array of inexpensive disks (RAID) unit.
In order to meet greater performance demands, DASD controllers must be capable of handling data at increasing rates. Designing multiple very high data rate channels within a DASD controller unit and, specifically, to and from a central cache memory is limited with current parallel bus structures. Such a parallel bus system in shown in FIG. 1.
One possible solution for increasing the data rate is to make the parallel bus wider by increasing the number of data wires. This results in several difficulties such as a greater number of traces on a printed circuit board (PCB) requiring valuable board real estate, additional driver/receiver pairs, additional connector pins to provide circuit card-to-circuit card interconnection and increased associated electrical power.
Another possible solution for increasing the data rate is to send parallel bus control signals on dedicated wires. These separate signals, called sideband signals, may signal the start of transmission, provide timing, specify intended receivers, request attention, or indicate success or failure. Using sideband signals increases the number of connecting wires and, hence, suffers from the same drawbacks as increasing the number of data wires.
Still another possible solution for increasing the data rate is to increase the clock rate used on an existing parallel bus. However, decreasing the time between clock edges is limited by the physics of parallel connecting devices. In particular, each device has an associated capacitance. The total capacitance is the sum of the individual capacitances and the distributed capacitance of the interconnecting trace. The velocity of propagation of a signal down the bus is inversely proportional to this total capacitance and, therefore, the clock switching speed is directly limited by the total capacitance.
A further possible solution for increasing the data rate is to use a currently available serial protocol for busing data within the DASD controller. Such protocols include SONET (Synchronous Optical NETwork), Fiber Channel, and USB (Universal Serial Bus). However, these protocols were designed primarily for connection between devices and not intradevice busses; and primarily for use with particular interconnection media such as fiber optic cable, coaxial cable, or twisted pairs. Therefore, use in PCB busses results in data transfer rates no greater than 200 megabytes per second, which is below the capabilities achievable using interconnection media for which the existing protocols were designed. Additionally, the latency inherent in these protocols is troublesome and difficult to reduce.
In addition to simply increasing the data rate on a DASD buss, data must be written to two different disks in a RAID 1 system. One solution with current parallel buses is to send the data twice, effectively halving the data transfer rate. Another solution is to provide multiple parallel paths, requiring twice the hardware. Still another solution is to construct a special protocol enabling two recipients to receive the same data, requiring more complex logic in the protocol engine and potential performance degradation.
What is needed is a bus system that can achieve increased data rates without incurring the problems associated with increasing the number of wires, using sideband signals, increasing the clock rate, or using current serial bus protocols. The ability to support RAID 1 should also be provided.